1. Field of the Invention
This invention relates to switching power supplies and in particular to a switching power supply with a current mode control loop.
2. Prior Art
Current mode controlled switching power supplies are well known. In a current mode controlled switching power supply, the output voltage from the power supply is measured and compared to a reference voltage. Any error signal resulting from a difference between the two voltages is then used to control the peak switch current from the power switch on a cycle-by-cycle basis. It is known that in a normal current mode controlled switching power supply a capacitor cannot be used to couple the input of the power transformer to the power switches because such a capacitor results in an instability which causes the power supply to latch up. The use of such a coupling capacitor is desirable to prevent transformer saturation due to DC currents through the transformer.
FIG. 1 illustrates a dual loop current mode switching power supply of the prior art and FIG. 2a illustrates a half bridge converter circuit wherein two capacitors replace two switching transistors normally present in a full bridge of a type known in the prior art. In the circuit of FIG. 1, the output voltage on lead 22 from the power supply (often called a "converter") is sent to error amplifier 25 on the inverting input lead 27a of amplifier 25. Voltage reference 28 is applied to the noninverting input lead 27b of error amplifier 25. The output signal from amplifier 25 comprises an error voltage which represents the difference between the voltage on output lead 22 and reference voltage 28. This error voltage controls the current source loop 30 which in turn controls the peak switch current from power switch 23 on a cycle-by-cycle basis. The second loop 30 includes a comparator 26 which senses the difference between the error voltage from error amplifier 25 and a signal produced by current sense circuit 27 proportional to the peak switch current from power switch 23 on a cycle-by-cycle basis. When the power switch 23 is configured as a push-pull circuit, loop 30 corrects for transformer imbalances caused by, for example, differences between storage times of switch transistors (such as transistors Q1 and Q2 in FIG. 2a), noise and load transients which can cause transformer flux saturation and thus excessive DC current in the switching transistors.
Different forms of dual loop current mode control have been utilized for their advantages of speed, performance and reliability. Unfortunately, none of these are usable with "half bridge" converter topologies, or with other push-pull topologies that are capacitor coupled to the output transformer. This is because the introduction of one or more capacitors to the circuit results in an instability which causes the system to latch up in a failure mode. FIG. 2a illustrates a typical capacitor coupled topology employing a half bridge. In FIG. 2a switching transistors Q1 and Q2 are driven by a control circuit and comprise part of power switch 23 shown in FIG. 1.
In the circuit of FIG. 2a when switch SW1 comprising transistor Q1 is on, current flows from the +V input lead through transistor Q1 and through the primary to node A. This current then charges capacitor C2 and discharges capacitor C1. When transistor Q1 shuts off and transistor Q2 comprising switch SW2 turns on, current I.sub.1 flows in the opposite direction and discharges capacitor C2 and charges capacitor C1. During the flow of the current I.sub.1 through the primary PRI in one direction or the other, current sense circuit 27 detects the magnitude of this current. Simultaneously with the current flow through the primary PRI, a current is generated in the secondary winding SEC of transformer T1. This secondary current is passed through a rectifier and a choke corresponding to choke 24 as shown in FIG. 1 and then stored on an output capacitor corresponding to C29 in FIG. 1.
One problem with the circuit of FIG. 2a is that while the voltage at node A theoretically should average precisely halfway between +V and -V, in reality the voltage on node A can easily deviate slightly from this ideal. The circuit then forces the voltage on node A either to approximately +V or -V depending upon the direction of the initial unbalance in this voltage. Typically, this takes between 3 and 20 cycles.
Transistors Q1 and Q2 each turn off only when the corresponding current I.sub.1 or I.sub.2 through the primary PRI reaches a maximum value as determined by the error voltage from amplifier 25. The length of time for this current to reach this maximum value depends upon the charge on C1 when Q1 turns on and the charge on C2 when Q2 turns on. The result is that the current I.sub.1 flows for a much longer duration when V1 is much less than V2, as shown in FIG. 3, than the current I.sub.2 in the other direction. Therefore the charges on capacitors C1 and C2 will continue to diverge in magnitude and ultimately most of the voltage across the half bridge circuit will be taken across capacitor C2 for the current imbalance shown in FIG. 3.
In any current mode control loop such as shown in FIG. 1, the switches in power switch 23 (corresponding to transistors Q1 and Q2 in FIG. 2a) are turned off at a control current that is the same for the positive and negative current flows I.sub.1 and I.sub.2 through the primary of transformer T1. Thus maximum current I.sub.1 and maximum current I.sub.2 as shown in FIG. 3 are the same and are set by the error voltage from error amplifier 25 (FIG. 1). If V1 and V2 are equal (i.e., the voltages across capacitor C1 and capacitor C2 are equal) the slopes S1 and S2 of the current pulses shown in FIG. 3 as illustrated will be equal because the slopes are approximately proportional to the voltages V1 and V2 across capacitors C1 and C2. These voltages control the rate of current rise in the output filter (corresponding to output choke 24 in FIG. 1) and the output transformer (corresponding to transformer T1 shown in FIG. 2a). This is not a stable situation as discussed above and is similar to a pencil balanced on its point. Just as any slight noise will cause the pencil to fall if there is a slight difference between V1 and V2 (for example if V2 is slightly greater than V1) the difference will increase until V2 is almost double its original value and V1 is almost zero. This occurs because a higher voltage across C2 causes a quicker rise (increase in the slope S2) of inductive current through the primary PRI of transformer T1 and a shortening of the on time of transistor W1. The opposite is true for the on-time of the current I.sub.1, through transistor Q1 with lower slope S1. Switch SW1 will eventually remain on until it is turned off other than by reaching its current limit.
Note that each transistor Q1 and Q2 is turned off when the current I.sub.1 or I.sub.2 equals Max I.sub.1 or Max I.sub.2 respectively. Max I.sub.1 has the same absolute magnitude as Max I.sub.2. If the voltage V2 across capacitor C2 is approximately the same value as the voltage +V to -V across the half bridge converter, when transistor Q2 turns on, the current through transistor Q2 from capacitor C2 will reach Max I.sub.2 in a very short time. Thus, the charge on capacitor C2 will not be substantially depleted before the signal from comparator 26 shuts off the transistor Q2. Transistor Q1 is then turned on. Unfortunately, the voltage V1 across capacitor C1 is very small. Therefore, the rate of rise of the current I.sub.1 through transistor Q1 is very low and consequently a long time will elapse before this current reaches the maximum current at which the signal from comparator 26 will shut off transistor Q1. Indeed, if capacitor C2 is charged to voltage V2 and V2 equals the voltage across the half bridge circuit (+V to -V), the current I.sub.1 will drop to zero rather than increase to Max I.sub.1. Thus, the half bridge converter will have "latched up" and will no longer switch unless a circuit is provided to switch Q1 automatically after the lapse of a given time. However, this still will not prevent the half bridge circuit from latching up with the voltage across one of the capacitors being grossly different from the voltage across the other capacitor.
In any event, within a few dozen switch cycles at most, the converter will latch up and provide very close to zero output current. It makes no difference if other control methods are used, such as fixed off time or hysteresis control of current level, for two examples. The above-described problem exists with any current turn off control that uses capacitive coupling such as capacitors C1 and C2 of FIG. 2a. Even a full bridge converter using current mode control will latch up if a capacitor is inserted in series with the primary of the output transformer. This precludes the utilization of a capacitor to prevent destructive currents under some transient or imbalance conditions in full bridge converters.